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			96 lines
		
	
	
		
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			96 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			HTML
		
	
	
	
	
	
<!doctype html>
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<title>CodeMirror: VHDL mode</title>
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<meta charset="utf-8"/>
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  <a href="https://codemirror.net"><h1>CodeMirror</h1><img id=logo src="../../doc/logo.png"></a>
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    <li><a href="../index.html">Language modes</a>
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    <li><a class=active href="#">VHDL</a>
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  </ul>
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</div>
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<article>
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<h2>VHDL mode</h2>
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<div><textarea id="code" name="code">
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY tb IS
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END tb;
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ARCHITECTURE behavior OF tb IS
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   --Inputs
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   signal a : unsigned(2 downto 0) := (others => '0');
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   signal b : unsigned(2 downto 0) := (others => '0');
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    --Outputs
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   signal a_eq_b : std_logic;
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   signal a_le_b : std_logic;
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   signal a_gt_b : std_logic;
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    signal i,j : integer;
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BEGIN
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    -- Instantiate the Unit Under Test (UUT)
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   uut: entity work.comparator PORT MAP (
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          a => a,
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          b => b,
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          a_eq_b => a_eq_b,
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          a_le_b => a_le_b,
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          a_gt_b => a_gt_b
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        );
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   -- Stimulus process
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   stim_proc: process
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   begin
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        for i in 0 to 8 loop
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            for j in 0 to 8 loop
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                a <= to_unsigned(i,3); --integer to unsigned type conversion
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                b <= to_unsigned(j,3);
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                wait for 10 ns;
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            end loop;
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        end loop;
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   end process;
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END;
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</textarea></div>
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</script>
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<p>
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Syntax highlighting and indentation for the VHDL language.
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<h2>Configuration options:</h2>
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  <ul>
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    <li><strong>atoms</strong> - List of atom words. Default: "null"</li>
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    <li><strong>hooks</strong> - List of meta hooks. Default: ["`", "$"]</li>
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<p><strong>MIME types defined:</strong> <code>text/x-vhdl</code>.</p>
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</article>
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